Open Source FPGAs
PULP: Open Hardware at the Edge of the IoT - PDF
Speaker: Davide Rossi, University of Bologna.
Abstract: The “internet of everything” envisions trillions of connected objects loaded with high-bandwidth sensors requiring massive amounts of local signal processing, fusion, pattern extraction and classification. While silicon access cost is naturally decreasing due to the twilight of the Moore’s law and thanks to the availability of cheap and efficient FPGAs, access to hardware IPs still represents a huge barrier for innovative start-ups and companies approaching the market of IoT. In this context, the recent growth of high-quality open source hardware IPs represents a promising way to surpass this barrier, paving the way for a number of exciting applications of open-source electronics. In this talk, I will describe the evolution of the open-source Parallel-Ultra-Low-Power (PULP) platform as well as opportunities and challenges for next generation open source computing systems.
Davide Rossi, received the PhD from the University of Bologna, Italy, in 2012. He has been a post doc researcher in the same university since 2015, where he currently holds an assistant professor position. His research interests focus on energy efficient digital architectures in the domain of heterogeneous and reconfigurable multi and many-core systems on a chip. This includes architectures, design implementation strategies, and runtime support to address performance, energy efficiency, and reliability issues of both high end embedded platforms and ultra-low-power computing platforms targeting the IoT domain. In these fields, he has published more than 100 paper in international peer-reviewed conferences and journals. He is member of IEEE and The Free and Open Source Silicon (FOSSI) Foundation. He is the recipient of the 2019 IEEE TCAD Donald O. Pederson Best Paper Award.
Scalable performance by scaling out FPGA systems via inexpensive interconnects and the open-source AXIOM software stack - PDF
Speaker: Roberto Giorgi.
Abstract: This presentation will introduce the "AXIOM software stack", which provides the possibility to distribute computations across a cluster of FPGAs by using the OmpSs programming model. OmpSs allows the programmer to increase the performance by either parallelizing the application on cores and nodes/boards of the cluster or by offloading a computation on an FPGA accelerator: the AXIOM project explored both the options and the combination of them. This open-source software, along the full software stack based on a standard Linux/Ubuntu 16.04 LTS distribution has been demonstrated on the AXIOM-board, which is based on the Zynq ZU9EG Ultrascale+ Soc. To further simplify the deployment and provide and inexpensive mean for connecting up to 255 boards, the AXIOM-board provides four USB-C connectors, each one capable of up to 18Gbps data transfer rate. This model permits to address the need of a scalable performance depending on the size of the problem, e.g., in the Smart Home in order to serve a building or an apartment, by using the same hardware and software platform, or in the Smart Videosurveillance.
Xilinx open-source research - PDF
Speaker: Cathal McCabe, Xilinx.
Abstract: Xilinx research labs have recently been working on a number of open-source research initiatives. PYNQ is a Python-based open-source productivity environment. PYNQ leverages Jupyter notebook and Jupyter lab, and allows developers to rapidly explore and prototype Xilinx embedded, and compute acceleration systems. FINN is an experimental open-source machine learning framework to explore deep neural network inference on FPGAs. It specifically targets quantized neural networks, with emphasis on generating dataflow-style architectures customized for each network. RapidWright is an open source gateway to backend tools in Vivado. RapidWright enables users to customize implementations to their unique challenges and provides a design methodology using pre-implemented modules. This presentation will give an overview of each of these projects including latest developments, future directions, opportunities, and how to get involved.
Cathal McCabe is a senior engineer in the Xilinx CTO department, where he manages the Xilinx University Program in EMEA. As part of this role he delivers training workshops for academics on the latest Xilinx tools and technologies. Most recently he has been working on the PYNQ project – a Python-based open-source productivity environment for Zynq and Zynq MPSoC. He is also responsible for academic and industrial partnerships, and special initiatives in the region. Before joining Xilinx, Cathal worked for the Science and Technology Facilities Council (STFC) in the UK, where he was the Europractice manager for FPGA, Embedded, and ESL design tools and flows and responsible for training on related topics.
RISC-V/CGRA-based open source SoC - PDF
Speaker: José T. de Sousa, IST/University of Lisbon and INESC-ID.
Abstract: Open Source Reconfigurable Computing (RC) is an interesting idea but there are many challenges to overcome before it becomes a reality. Reconfigurable Computing is normally associated with FPGAs, so one is immediately led to the idea of Open Source FPGAs. There have been a few attempts to build open source FPGA toolchains . Thus, the first question raised by this talk is whether an open source FPGA toolchain is possible without an open source FPGA hardware architecture. It is concluded that it is not possible: an open source FPGA toolchain requires an open source hardware architecture in order to be successful. Given the fact that FPGAs are still one of the few full-custom digital circuits, the development of FPGA architectures and their post-silicon characterization is prohibitively expensive and can only be afforded by a handful of companies. Hence, it is unlikely that such full-custom designs will be open sourced . It is more likely that a synthesizable FPGA architecture that can be mapped to standard cell technologies is open sourced [4,5]. This would lower the entry barrier considerably and clear the way for open source FPGAs. However, RC is not only about FPGAs. Coarse Grained Reconfigurable Arrays (CGRAs), although not as well known as FPGAs, are an alternative reconfigurable fabric. CGRAs, as the name indicates, use coarser grained blocks that operate at the word level in contrast with FPGAs that operate at the bit level. CGRAs are not as flexible as FPGAs but they are considerably easier to open source. Normally, CGRAs are home-grown and there are no commercial solutions in the form of chips or Intellectual Property (IP) modules. CGRAs are normally single-clock fully synchronous designs that avoid the timing issues that characterize FPGAs like the need to generate and operate multiple clock domains and the need to achieve timing closure of the designs. They are used to map program loops with heavy computations to the reconfigurable fabric rather than mapping generic hardware circuits described using HDLs. The architecture-toolchain dialectic is easier to meet with CGRAs and therefore this talk focuses on the topic of open source CGRAs. Versat , an open source CGRA being developed at INESC-ID since 2015, and its C++ programming API which for the moment replaces a full-fledged compiler, is used as an example in this presentation. FPGAs have become considerably heterogenous over time, including RAM blocks (BRAM), Digital Signal Processing (DSP, normally a combination of multiplier and adder circuits), and von-Neumann CPUs which efficiently implement control structures. CGRAs are also heterogeneous and also need control CPUs. For an open source CGRA, the natural choice of a control CPU is the well-known RISC-V Instruction Set Architecture (ISA) . Open source processor hardware has been sought intensively in the last 3 decades but only recently, with the advent of the RISC-V ISA, it has become mainstream. Being a standard, the RISC-V ISA stabilizes the open source development of compliant hardware architectures and toolchains, which, as stressed in this talk, is a prerequisite for the hardware/software open source community to thrive. Moreover, CGRAs and RISC-V CPUs can target multiple FPGA architectures avoiding the vendor lock-in problem. When mapped to FPGAs as an overlay, CGRAs offer faster reconfiguration in exchange for FPGA real estate. Highly heterogeneous FPGA designs combining RISC-V CPUs, CGRAs and data flow engines created using high-level programming languages, such as Maxeler’s SPL , have the potential to lead RC into the programming mainstream, away from the hardware design stigma and closer to the open source paradigm.
José T. de Sousa is a professor at IST-University of Lisbon and a researcher at INESC-ID Lisbon (1999-present). He holds a PhD degree from Imperial College London (1998). He worked at Bell Labs, Murray Hill, N.J. (1998-1999). He holds 4 international patents, is co-author of the book entitled Boundary-Scan Interconnect Diagnosis, was General Chair of the 2013 Field Programmable Logic and Applications Conference, co-editor of the respective Springer LNCS series book and of a related special issue on the IEEE Transactions on Computers journal. Dr. de Sousa has published more than 70 technical papers in international journals and conferences. He was co-founder and CEO of Coreworks, a semiconductor intellectual property company (2001-2013). His specialties are digital circuit design, hardware/software architecture, technical team management and semiconductor IP marketing and sales.
FPGAs in Space
Reconfigurable Fault-Tolerant High-Performance Computing on Board Satellites
Speaker: Tanya Vladimirova.
Abstract: Current and future space missions demand highly reliable on-board computing systems, which are capable of carrying out high-performance data processing. Space systems benefit enormously from using reconfigurable programmable logic devices and their high-performance capabilities. However, SRAM-based FPGAs are susceptible to single-event upsets (SEUs) induced by radiation and need to be protected in the harsh space radiation environment. In this talk a new fault-tolerant distributed on-board computing platform will be presented, which avoids catastrophic system failures through intelligent use of computing resources for fault-tolerance. The platform provides a scalable and extendable computing architecture. It is inherently fault-tolerant due to mapping of application tasks to multiple processors. Tasks are migrated and computing nodes are reconfigured, protecting the system against a node failure. A new fault detection, isolation, and recovery (FDIR) methodology will also be presented which provides a generalized and unified framework for SEU mitigation. The proposed methodology offers a new capability allowing the analysis of a circuit without a detailed knowledge of its internal structure. The methodology is implemented as a set of tools integrated together and is fully tested using a case study based on a typical satellite payload data streaming system.
Prof. Tanya Vladimirova MEng MSc PhD CEng FIET SMIEEE MACM FHEA was educated in Bulgaria and Russia. She founded and led the VLSI Design and Embedded Systems (VDES) research group at the Surrey Space Centre (SSC), Department of Electronic Engineering, University of Surrey, during 1998-2011. The VDES group became internationally recognised for pioneering new ideas and novel accomplishments, inspiring follow-up research activities in various space research centres worldwide, e.g.: the First design of a reconfigurable system-on-chip based on-board computer (Reported at MAPLD’2000); the First satellite on a printed circuit board (PCBSat) design (Reported at IAC’2006); the First satellite-on-a-chip feasibility study (Reported at 5th ESA Round table on MNT for Space, 2005);the First low power Radiation Hardening by Design method based on the combined use of asynchronous logic (Reported at ISCAS’2008); the First model of space based wireless sensor networks sharing a distributed computing platform (Reported at AHS’2006); the First fault-tolerant AES algorithm for encryption of Earth observation satellite images (Reported at ICCST’2006); the First implementation of the lossless compression CCSDS algorithm for multispectral satellite images on a reconfigurable FPGA (Reported at AHS’2008); the First feasibility study on flood monitoring on board small satellites (Reported at ACRS’2005).
FPGA acceleration for vision-based navigation in space applications: devices, algorithms, use cases - PDF
Speaker: Dimitrios Soudris.
Abstract: High performance embedded computing in space is becoming a vital prerequisite for future applications, especially those relying on intensive Digital Signal Processing (DSP). Conventional space-grade CPUs are 1-2 orders of magnitude slower than the new application requirements. Therefore, considerable effort is now being spent on designing new avionics to include hardware accelerators. The Field-Programmable-Gate-Arrays (FPGA) are gaining ground due to various advantages, such as reconfigurability, algorithmic parallelization, performance per Watt, radiation hardening techniques, etc. Our lab is involved in a number of ESA activities related to the use of FPGA and novel DSP chips in space applications. We study all options for leveraging this technology in space and we demonstrate its benefits on specific use cases. We design architectures and accelerate DSP algorithms on a variety of platforms, either Space-Grade or Commercial-Off-The-Shelf, with Single-, Multi-, and System-on-Chip devices.
Performance and Reliability of Reconfigurable High Density Rad-Hard FPGAs for Space
Speaker: Luca Sterpone.
Abstract: In the framework of the EU Project VEGAS, a set of CAD tools able to elaborate and analyse the netlist generated by FPGA implementation tools have been developed aiming at evaluating the performance in harsh radiation environments such as space and avionics. In this presentation we will focus on the development of two methods: a reconfigurable- oriented analyser that is able to evaluate the reconfigurability performances in the circumstances of radiation effects, and a radiation effect simulator, that it is able to allow the simulation of reconfigurable circuits on FPGAs in the presence of Total Ionizing Dose (TID) and Single Event Effects (SEEs). The tools will be applied to three different categories of FPGAs for space: RTG4 from Microsemi, Space-grade Virtex-5QV from Xilinx and NG-MEDIUM from NanoXplore. The presentation will provide characteristics and methodology that can be applied on rad-hard FPGAs for the analysis of performance of the implemented circuits aiming at the effective usage of reconfiguration in space. A demonstration of the possible application on the verification of robustness and mitigation techniques applied on a set of test-bench circuits will be provided. Experimental results obtained by simulation, emulation and radiation tests will be commented and discussed in details.
Increasing reliability of commercial reconfigurable MPSoC FPGAs for space applications - PDF
Speaker: Eduardo de la Torre.
Abstract: The combination of more demanding computation requirements with even newer important cost reductions derived from the increasing number of competitors for the space business, makes traditional on-board-processing solutions a reliable but expensive alternative. The need of reconfigurability at both HW and SW levels to adapt to fast evolving communication protocols, scientific missions that need to adapt ‘on the spot’ are, among other triggers, reasons to implement reconfigurability and self-adaptivity on the computing platforms. An advantage of accounting with reconfigurability is that this feature can, to some extent, increase the reliability-related features of the system, by adopting capabilities to detect and repair hardware faults. Commercial MPSoCs combining programmable logic with processors are, therefore, suitable candidates to solve the mentioned problems. Their inherently weak resilience to faults can be alleviated with fault tolerance and error mitigation techniques and suitable repair methods. Under this scenario, it is important to have strcutrued techniques, as independent of the mission as possible, as well as validation methods that will allow to measure parameters such as reliability (how resistant is the system to faults), availability (how fast these faults can be identified, isolated and repaired), or even performability (what functions the system can do even in the presence of permanent faults). In this talk we present a system architecture set-up that includes a variety of fault mitigation techniques, combined with an embedded verification and validation platform, all embedded in a Zynq UltraScale+ device. The architecture and system set-up are aimed at simplifying the development of new missions, while the validation platform is geared towards measuring performance and reliability parameters under real-time constraints and fault injection.
GoAhead for using FPGAs in Space Applications - PDF
Speaker: Dirk Koch.
Abstract: GoAhead is a tool that is originally designed for implementing partially reconfigurable systems. In its initial release, it supports all Xilinx FPGA devices which are enabled in the ISE tools through the vendor specific XDL API (including rad-hard Virtex-5QV FPGAs). In its recent release, GoAhead works with the Xilinx Vivado tool through the TCL API and it supports all 7 Series and UltraScale FPGA families. In this talk, we will provide a few examples of how GoAhead was/is used in the H2020 projects ECOSCALE and EuroEXA to modularize the design of large scale FPGA systems and to implement fault tolerance. GoAhead is also used for security research in our reconfigurable FPGA Accelerator Sandboxing (rFAS) project. The methodologies used in these projects can serve as templates to perform the specific implementation needs when using FPGAs in space applications and we will show a corresponding system that was built with GoAhead. This system is supporting the isolation design flow (IDF) methodology together with partial reconfiguration in a way such that the same partial module bitstream can be relocated to serve all redundant accelerator instances. GoAhead is also able to constrain routing such that signal paths from redundant instances to voters follow IDF rules. Moreover, together with the configuration bitstream manipulation tool BitMan, we can precisely analyze the sensitivity of configuration bits to the netlist that a Xilinx FPGA is implementing. With this, GoAhead complements the Xilinx vendor tools with unique features that are very common in space applications. Finally, the talk will briefly show recent research at the University of Manchester on open-source FPGAs. This includes a) the EFCAD (Embedded FPGA CAD) tool flow that allows Zynq UltraScale+ to compile Verilog to a partially reconfigurable bitstream and b) work on a RISC-V system integrating an embedded FPGA fabric that is currently in production at TSMC.
Dirk Koch is a senior lecturer in the Advanced Processor Technologies Group at the University of Manchester. His main research interests are on run-time reconfigurable systems based on FPGAs, embedded systems, computer architecture, VLSI and hardware security. Dirk developed techniques and tools for self-adaptive distributed embedded control systems based on FPGAs. Current research projects include database acceleration using FPGAs-based stream processing, HPC and exascale computing, as well as reconfigurable instruction set extensions for CPUs and using FPGAs in datacenters. Dirk Koch is author of the book "Partial Reconfiguration on FPGAs" and a co-editor of the book "FPGAs for Software Programmers".