Porto, Portugal            October 10-12, 2018     
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Special Sessions

Special Session on Signal Processing and Architectures for 5G Wireless Systems

Arnaldo S. R. Oliveira
José Neto Vieira (DETI-UA/IT-Aveiro)

It is widely accepted that the major pillars and differentiating features of 5G systems are:

  • Enhanced mobile broadband for high data rate demanding applications
  • Massive low data rate and machine type communications for the IoT
  • Ultra-reliable and low latency communications for real-time and safety critical applications

These types of communication will require considerable improvements and breakthroughs in terms of data rate, network capacity, connection density, end-to-end latency, spectral efficiency, power consumption, mobility, coverage and cost. Some key technologies that are being evaluated for these purposes include massive MIMO, 3D beamforming, ultra-dense networks, new physical layer waveforms and channel access mechanisms (e.g. full-duplex techniques), usage of millimeter waves spectrum bands and new paradigms in the core and access network architectures (e.g. Cloud Radio Access Network approaches).

This Special Section is devoted to the presentation and discussion of advanced signal processing algorithms, novel implementation architectures, design languages and tools that will support the development of 5G wireless communications systems. Prospective authors are encouraged to submit original and high quality papers in one or more of the following topics focused on 5G wireless systems:

  • Software defined and cognitive radio approaches
  • Sparse signal processing concepts for efficient 5G
  • Spatial signal processing for 5G
  • Modulation, coding and waveform for 5G
  • Signal processing for new spectrum opportunities
  • Modelling, simulation and profiling techniques
  • Validation and test approaches and tools
  • Processing architectures for 5G systems implementation
    • Specialized and/or reconfigurable
    • Low power
    • (Massively) parallel
  • Languages and compilation tools for 5G systems design
  • Prototyping devices and technologies for 5G
  • All (most) digital transceiver architectures
  • Agile and/or wideband enabled transceiver architectures and design
  • Low power and battery-less transceivers
  • Backhaul and fronthaul interfacing, processing and optimization
  • Demonstrators and testbeds

Special Session on Energy-Aware Architectures and Systems for Signal, Image and Video Processing

Nuno Roma (INESC-ID, IST, University of Lisbon – Portugal)
Luciano Agostini (GACI, CDTec, Federal University of Pelotas – Brazil)

Power and energy consumption have gradually become a prevailing aspect in the implementation of signal, image and video processing systems. As a result, performance and energy efficiency optimization has become a fundamental constraint and requisite, embracing not only the processor architectures (homogeneous/heterogeneous many-core CPUs), but also the several accelerators and co-processors that may coexist in the processing system (e.g., FPGAs, ASICs, GPUs, APUs, etc.). In particular, the development of energy saving methodologies is now regarded as a fundamental issue in the embedded domain, including also the mobile, hand-held and wireless applications.

The need to satisfy the required performance levels, allied with energy, power and even thermal constraints requires innovative solutions to attain an effective optimization of the offered throughput and/or minimization of the power/energy consumption. Among many other research directions, this challenge naturally involves the design of high performance and energy-efficient architectures and communication infrastructures, as well as the development of novel algorithms and tools.

The goal of this special session is to bring together active researchers who are interested in prevailing issues and prominent challenges related to the design of energy-aware architectures and systems for signal, image and video processing.

The topics of interest include (but are not limited to) the following:

  • Architecture trends for performance and energy efficiency
  • Heterogeneous and parallel processing architectures
  • Run-time reconfiguration/adaptation and dynamic scalability
  • Accelerator co-design (FPGAs, ASICs, GPUs, APUs, etc.)
  • Approximate computing techniques and architectures
  • Run-time power/energy monitoring and sensing
  • Performance, power, energy and heat/temperature models
  • Dynamic Voltage and Frequency Scaling (DVFS)
  • Power/clock gating strategies
  • Energy/power management and control
  • Algorithms optimization towards energy/power efficiency

Both theoretical papers and papers describing systems implementations and real-world practical experiences will be welcome.

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