A second Renaissance or Disaster for Reconfigurable Computing?

Speaker: Georgi Gaydadjiev - University of Groningen, The Netherlands

Abstract: With quantum computers remaining utopian for yet another 10 to 15 years, the "neuromorphic" computing stalled in its infancy and the conventional CMOS technology feature sizes bumping against the reality of Silicon inter-atomic distances, the only technological option left able to deliver the expected improvements in computers productivity is Reconfigurable Custom Computing. This situation forms a tremendous opportunity and a significant headache at the same time since it requires community-wide coordinated efforts in order to translate the technological potential into practically useful computing systems. The sad reality is that both Academia and Industry keep working in isolation and focusing on various tiny niches that typically can not be easily migrated to other domains. The design of practically useful reconfigurable accelerators remains too complex for engineers with hardware background, while software developers fail short in their understanding of parallel computing timing, space and custom data representation. This talk will present the author's personal opinion about the challenges ahead and how they can be potentially addressed in order to deliver the so-needed practical solutions for the upcoming decade. This is sadly a huge responsibility for all of us since most of all long-promised alternatives will not become a reality soon.

Short bio

Georgi Gaydadjiev is a Full Professor in Innovative Computer Architectures at the University of Groningen in the Netherlands and a honorary visiting professor at the Department of Computing of Imperial College London. Between 2014 and 2019 Georgi was the VP of Dataflow Software Engineering of Maxeler Technologies Ltd in London and the founding Director of Maxeler IoT-Labs BV in Delft, the Netherlands. Prior to 2014 Georgi spent more than 25 years on research and development of various computing systems in Industry and Academia. He holds best papers from ACM/SIGARCH International Conference on Supercomputing (ICS) and the USENIX/SAGE Large Installation System Administration (LISA) conference. In 1999 one of his projects at CPS BV in the Netherlands received the Design & Engineering Showcase Award at the annual Consumer Electronics Show (CES) in Las Vegas, USA. Georgi is a HiPEAC member from day one of the network and was the main responsible for the very first editions of WRC.

Embedded Reconfigurable System Integration – Decentral Adaptivity, Reliability and Intelligence as Enablers

Speaker: Juergen Becker - KIT Germany

Abstract: The field of dynamically reconfigurable electronic systems, incl. embedded multi-core (MC) and cyber-physical systems (CPS) integration, is still emerging and challenging the silicon technologies. Here, on one side increasing monolythic integration of cooperating computational and physical elements is necessary, e. g. in embedded and smart on-demand automatized environments as diverse as space, avionics, automotive, chemical processes, civil infrastructure, energy, healthcare, manufacturing (Industry 4.0), transportation, entertainment, and communication/consumer appliances. On the other side, in the future within complex dynamically reconfigurable and multi-domain electronic system integration the emphasis tends to be more and more dependent on distributed real-time and embedded High-Performance Computing (HPC) availability. This results in the strong demand of newly operating decentralized/centralized intelligent, interconnected, and silicon technology integrated solutions, subject to increased performance needs to facilitate computationally intensive algorithms, power consumption to be minimized for mobile devices, and sufficient degrees of reliability and verifiability to employ digital systems in safety-critical environments. Existing technology must evolve in order to meet such high requirements, whereas open source hardware and artificial intelligence (AI) could alsoplay key roles in this process. Multipurpose adaptivity and reliability are crucial, especially in scaling down silicon technologies according to Moore for future processor technologies incl. dynamically reconfigurable accelerators and embedded HPC architectures. This requires new solutions for parallel programming, reference technology platforms (RTP) and standardized tool flows. The talk will discuss the challenges of heterogenous reconfigurable multi-core platforms incl. reliable SoC and scalable hardware/software integration in the context of several project initiatives like ARAMiS (Automotive, Railway and Avionics Multicore Systems - http://www.projekt-aramis.de, https://www.aramis2.com ), EPI (European Processor Initiative), among others.

Short bio

Jürgen Becker received the Diploma and Ph.D. (Dr.-Ing.) degree from Technical University Kaiserslautern, Germany. He is full professor for embedded electronic systems and Head of the Institute for Information Processing Technologies (ITIV) at the Karlsruhe Institute of Technology (KIT). From 2005-2009 he has been appointed as Vice President for Education at Universitaet Karlsruhe (TH) and Chief Higher Education Officer (CHEO) at KIT from 2009-2012. Since 2012 till 2014 he served as Secretary General of CLUSTER, an association of 12 leading Technical Universities in Europe. His research interests include Hardware/Software Systems-on-Chip (SoC), Cyber-Physical Systems (CPS), Heterogenous Multicore (MC) Architectures and Design Methods, Reconfigurable Computing, with application in Embedded Systems (Automotive, Industry 4.0, Avionics, HPC Scientific Applications incl. Physics Detector Experiments). He authored more than 400 papers in peer-reviewed international journals and conferences. Prof. Becker is active in numerous international conferences, as Chairman in TPC & Steering Commitees, e. g. IEEE ISVLSI, IEEE SOCC, RAW, FPL, PATMOS, IFIP VLSI-SoC, DATE, SBCCI, ARC, FCCM, FPT, among others.

Software-Transparent Adaptive Processor Architecture Based on Coarse-Grained Reconfigurable Arrays

Speaker: Marcelo Brandalero - Brandenburg University of Technology (B-TU), Germany

Abstract: Heterogeneous Systems-on-Chip (SoCs) containing application-specific accelerators can lead to orders-of-magnitude increase in performance and energy efficiency compared to general-purpose processors. However, such a form of static specialization is hardly the best solution for Internet-of-Things (IoT), a scenario where, despite tight power constraints, applications are continuously evolving over time and the devices must endure for years of active operation. Moreover, to support the deployment of the IoT revolution, low cost is key - both from the software as well as the hardware perspective. In this talk, a framework for the generation of adaptive hardware architectures based on a Coarse-Grained Reconfigurable Accelerator (CGRA) will be presented. These architectures can automatically accelerate RISC-V code running in a low-power processor, without any changes to the software development flow, and can incorporate additional techniques for power savings and for automatically mitigating aging effects and tolerating faults. In doing so, the hardware development process is simplified, and programmers are exposed to a single uniform Instruction Set Architecture (ISA). The talk will present the experimental results and future directions on software-transparent and adaptive processor architectures.

Short bio

Marcelo Brandalero received his Dr. Degree in Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS) in Porto Alegre, Brazil, in 2019, and is currently a Senior Research Scientist at the Brandenburg University of Technology Cottbus-Senftenberg, in Germany. His research interests cover computer architecture, emphasizing reconfigurable architectures, low-power design, and approximate computing.

Cosmic Rays Come Down to Earth – The Problem of Neutrons at Ground Level

Speaker: Chris Frost - STFC Rutherford Appleton Laboratory, UK

Abstract: Radiation in space resulting from energetic solar and cosmic-ray particles is known and expected to cause problems for electronic system deployed in that harsh environment. What is less appreciated is that those same particles also interact with the Earth’s atmosphere to generate showers of high energy secondary particles at ground level and flight altitude, one of which, in particular, has emerged over the last few decades to become a significant problem for modern electronics’ reliability– the neutron. To address this problem the UK's ISIS Neutron and Muon Source designed and now operates ChipIr, a fast-neutron beamline that mimics the atmospheric-like neutron spectrum in the 1-800MeV regime, but with a highly enhanced neutron flux. Using this instrument, industrial and academic researchers perform accelerated fast-neutron testing on a wide variety of electronics to understand the detrimental effects of the natural atmospheric cosmic-ray neutrons on their device and systems and to mitigate their effects. This presentation will discuss the nature of the secondary atmospheric radiation, the neutron’s disruptive effect on electronics, how ChipIr was developed and incorporated onto an existing spallation target station at ISIS and finally how it can be used to address problems in the electronics' industrial sector.

Short bio

Christopher Frost is an Individual Merit Scientist at the ISIS Facility, Rutherford Appleton Laboratory, UK. He gained his Ph.D from Cambridge University, UK in 1995, where he used neutron scattering techniques to research the then new ‘high-temperature’ superconducting materials. He joined the Rutherford Appleton Laboratory in 1998 following a post-doc with Warwick University to develop and build innovative new neutron-scatting instrumentation to further pursue this research. Around 2007, he became interested in the emergent problem of the effect of cosmic rays on the reliability of avionics and electronics and how the accelerator based ISIS Facility could provide a solution for the UK. Working with industry he developed and built ChipIr a new neutron irradiation facility for testing device and system reliability which now works right across the electronics industry; tackling problems in areas such as driverless-cars, nuclear robotics, electric vehicles, internet infrastructure and avionic systems. Christopher is an author on over 140 papers in neutron science, regularly gives seminars and talks on the effect of cosmic rays on our modern electronic dominated lives and takes part in many outreach activities to engage the next generation in science and technology.

Artificial Intelligence for Space: New Challenges for the Reconfigurable Computing Paradigm

Speaker: Luca Sterpone - Politecnico di Torino, Italy

Abstract: Artificial Intelligence (AI) includes a large number of techniques that enable computing architectures to mimic intelligence such as the systems embedded in autonomous flying vehicle. Modern Neural Networks (NNs) have grown drastically in the recent five years, leading to the adoption of embedded circuits able to offer elevated computational power. AI implmenetations for space are still rarely used in autonomous space missions, since power and safety requirements are limiting the wide adoption of this techniques. Thanks to the possibility to reconfigure and to adapt the computational tasks on-site, Reconfigurable Computing is, again, facing a new application challenge towards enabling AI computation in space. In this talk, we will explore design and testing methodologies applied to implement NN on FPGA for space. We will present an hybrid platform for emulating the hardware accelerator used by specific solution under test. Furthermore, we will present the total and partial reconfiguration trade-off of a Convolutional Neural Network (CNN) suitable for deep space missions implemented on commercial and radiation hardened FPGAs. Finally, the obtained results are compared with a traditional software-level design and testing methods.

Short bio

Luca Sterpone received the MS and PhD degrees in computer engineering from Politecnico di Torino, Italy, in 2003 and 2007, respectively. He is currently Vice-Head of the Department of Control and Computer Engineering, Politecnico di Torino. His current research interests include reconfigurable computing, computer-aided design algorithms, fault tolerance architectures and artificial intelligence for space missions. He is author of more than 190 papers and he received several awards for his research activities.

Process Variability Analysis & Mitigation in State-of-the-Art FPGAs via Adaptive Reconfiguration Frameworks

Speaker: George Lentaris - NTUA, Greece

Abstract: The mitigation of process variability becomes critical as the FPGA technology nodes scale-down. From a user's perspective, the classical approach of applying conservative guard-bands leads to considerable performance loss, both in terms of throughput and power consumption. This hidden potential of many commercial off-the-shelf FPGAs could be harvested on a per device basis, in-the-field, by developing novel customization tools and adapting the FPGA operation to each application during the lifetime of a chip. As a prerequisite, a detailed analysis of chip variability must be performed before devising reconfiguration and adaptation techniques. We study the process variability of logic, interconnect and arithmetic/DSP resources in commercial 28nm and 16nm FPGAs. We develop soft-macro sensors for distinct FPGA resources and we deploy them across the fabric to measure intra-die and inter-die variation. We use the results to create signature maps and characterize each die. We decouple the variability to systematic and stochastic parts, we test under various voltages and temperatures, and we correlate the maps of different resources to strengthen our evaluation. Additionally, we correlate the performance of actual benchmarks/circuits with our Ring-Oscillators maps. Based on our custom sensing networks that can also operate in parallel to a user's design, we propose a framework to automatically characterize the user’s device, to conditionally place a given design on the most efficient region/chip and, afterwards, to scale its frequency and/or voltage according to user requirements even during operation. Our adaptation scheme targets the improvement of throughput and/or power consumption without hindering functionality. Our experimental evaluation relies on 20 FPGAs of 28nm Xilinx technology and 4 XCZU7EV FPGAs of 16nm technology node. The results showed significant intra- and inter-die variability, e.g., 13% intra-die and 30% inter-die for the former set of FPGAs. Our framework can lead up to 14.7% average throughput gain by exploiting variability or even up to double throughput by also customizing the guard-band, whereas the power consumption can be decreased by up to 28%.

Short bio

Dr George Lentaris is a senior research associate at Microlab, National Technical University of Athens (NTUA/Greece), working on high performance embedded computing. His work includes HW/SW co-design on single-/multi-/SoC-FPGA and DSP platforms to accelerate a variety of computer vision and telecommunication algorithms, as well as process variability and reliability of FPGA devices (including radiation testing). He holds a PhD in Computing from the National & Kapodistrian University of Athens/Greece ("Parallel Architectures and Algorithms for Digital Signal and Image Processing", NKUA, 2011), as well as two MSc degrees in "Logic, Algorithms, and Computation" and in "Electronic Automation", with a BSc in Physics. In the past decade, he has published >40 papers in the aforementioned domains and has participated in >10 European projects, both for the European Space Agency and for H2020. He also serves as a regular reviewer for international journals and as a teaching associate at NKUA and UNIWA, Greece.

Process Variability Analysis & Mitigation in State-of-the-Art FPGAs via Adaptive Reconfiguration Frameworks

Speaker: George Lentaris - NTUA, Greece

Abstract: The mitigation of process variability becomes critical as the FPGA technology nodes scale-down. From a user's perspective, the classical approach of applying conservative guard-bands leads to considerable performance loss, both in terms of throughput and power consumption. This hidden potential of many commercial off-the-shelf FPGAs could be harvested on a per device basis, in-the-field, by developing novel customization tools and adapting the FPGA operation to each application during the lifetime of a chip. As a prerequisite, a detailed analysis of chip variability must be performed before devising reconfiguration and adaptation techniques. We study the process variability of logic, interconnect and arithmetic/DSP resources in commercial 28nm and 16nm FPGAs. We develop soft-macro sensors for distinct FPGA resources and we deploy them across the fabric to measure intra-die and inter-die variation. We use the results to create signature maps and characterize each die. We decouple the variability to systematic and stochastic parts, we test under various voltages and temperatures, and we correlate the maps of different resources to strengthen our evaluation. Additionally, we correlate the performance of actual benchmarks/circuits with our Ring-Oscillators maps. Based on our custom sensing networks that can also operate in parallel to a user's design, we propose a framework to automatically characterize the user’s device, to conditionally place a given design on the most efficient region/chip and, afterwards, to scale its frequency and/or voltage according to user requirements even during operation. Our adaptation scheme targets the improvement of throughput and/or power consumption without hindering functionality. Our experimental evaluation relies on 20 FPGAs of 28nm Xilinx technology and 4 XCZU7EV FPGAs of 16nm technology node. The results showed significant intra- and inter-die variability, e.g., 13% intra-die and 30% inter-die for the former set of FPGAs. Our framework can lead up to 14.7% average throughput gain by exploiting variability or even up to double throughput by also customizing the guard-band, whereas the power consumption can be decreased by up to 28%.

Short bio

Dr George Lentaris is a senior research associate at Microlab, National Technical University of Athens (NTUA/Greece), working on high performance embedded computing. His work includes HW/SW co-design on single-/multi-/SoC-FPGA and DSP platforms to accelerate a variety of computer vision and telecommunication algorithms, as well as process variability and reliability of FPGA devices (including radiation testing). He holds a PhD in Computing from the National & Kapodistrian University of Athens/Greece ("Parallel Architectures and Algorithms for Digital Signal and Image Processing", NKUA, 2011), as well as two MSc degrees in "Logic, Algorithms, and Computation" and in "Electronic Automation", with a BSc in Physics. In the past decade, he has published >40 papers in the aforementioned domains and has participated in >10 European projects, both for the European Space Agency and for H2020. He also serves as a regular reviewer for international journals and as a teaching associate at NKUA and UNIWA, Greece.

RapidWright: An Open Source Framework for the Domain-specific Era

Speaker: Alireza Kaviani - Xilinx, USA

Abstract: As intrinsic silicon performance growth stagnates, new heterogenous strategies are being adopted to meet the world’s insatiable demand for compute. Customized architectures and data movement solutions are quickly becoming a necessity to help fill the performance void as we transition to an era of domain-specific acceleration. Additional complexity mounts with the need to swap between multiple sets of accelerators at runtime or run multiple instances simultaneously. FPGAs provide an attractive platform to enable domain specific acceleration due to their reconfigurable nature. To take advantage of this significant opportunity, we present RapidWright, an open source framework for Xilinx FPGAs that enables a domain-specific approach to implementation. RapidWright brings key capabilities such as reusability and relocate-ability of placed and routed implementations all within a customizable framework enabling a new class of accelerator development. In this talk, we describe RapidWright and its latest capabilities in addition to current and future engagements in the open source community.

Short bio

Alireza Kaviani is a distinguished Engineer at Xilinx Research Labs with a focus on the next generation FPGA architectures and tools. He has more than 20 years of FPGA and ASIC industry experience in the areas of architecture, tools, IC design, and applications. Alireza has authored more than 50 patents and publications in a number of areas, including clocking, asynchronous design, FPGA architecture and CAD tools. He holds a PhD degree from University of Toronto in Electrical and Computer Engineering.

Low energy machine learning

Speaker: Luigi Carro - UFRGS, Brazil

Abstract: Machine learning has blossomed, and everyday life nowadays is strongly based on some sort of iteration with hidden or explicit computers. Dealing with a huge amount of data, ML algorithms require high performance computers, and even some special architectures. However, the energy consumption of most ML algorithms is extremely high. This causes problems in the embedded domain, but also in servers, given the amount of people possibly using ML services. Traditional solutions of developing accelerators have been popular in the past 10 years, but they require huge NRE costs, and changing the software stack might prove also a bad strategy. As AI spreading only aggravates this problem,new solutions must be sought to provide not only high performance, but low energy as well, in order to sustain the growth of these new applications. In this talk we will discuss some possible steps in this direction, with minimal software and hardware modifications.

Short bio

Luigi Carro received the Electrical Engineering and the MSc degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Dr. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a full professor at the Applied Informatics Department at the Informatics Institute of UFRGS, in charge of Computer Architecture and Organization. He has advised more than 20 graduate students, and has published more than 150 technical papers on those topics. He has authored the book Digital systems Design and Prototyping (2001-in Portuguese) and is the co-author of Fault-Tolerance Techniques for SRAM-based FPGAs (2006-Springer), Dynamic Reconfigurable Architectures and Transparent optimization Techniques (2010-Springer) and Adaptive Systems (Springer 2012). In 2007 he received the prize FAPERGS - Researcher of the year in Computer Science.

System-Level Design of Adaptive Multiprocessor System-on-Chip for Resilient Systems

Speaker: Christophe Bobda - University of Florida, USA

Abstract: Technology scaling due to decreasing size of transistors has led the transition from single superscalar processors to multiprocessor system on chip (MPSoC) in a wide range of critical cyber-physical systems (CPS), including unmanned ground and air vehicles and SmartGrid, and thereby critically depend on the reliability and dependability of micro-and nano-electronic components. While software faults used to be the main source of concern, for example in automotive electronic systems, digital hardware has become a main source of faults since about 2010. This is due in particular because of feature size of integrated circuits approaching 10 nm horizontally and single layers of atoms vertically. As result, the long-term dependable service of multi-core processor in safety-critical applications is no longer guaranteed. Resilience-aware computing aims at designing and deploying systems that can withstand the successful exploitation of vulnerabilities and continue to meet mission goals. In the effort to reduce development cost and time-to-market, MPSoC designs are trending towards a heavy utilization of third-party Intellectual Property (IP) cores. Besides the challenges of correct integration of components from different vendor, this outsourcing of IP design to a third-party opens the door for potential introduction of malicious components. Traditional fault tolerant systems that uses redundancy based on probability of component failure fall short to address future challenges, due to the difficulty of verifying the probability of attack and successful exploitation of system vulnerability. This talk addresses system-level-design of secured system-on-chips through a tighter integration of user-specified resiliency requirements and objectives in the hardware/software design process. The talkl discuss generic models and tools to capture and quantify resilienc in MPSoC, along with protocols that automatically generate the hardware/software security infrastructure.

Short bio

Professor Bobda received the Licence in mathematics from the University of Yaounde, Cameroon, in 1992, the diploma of computer science and the Ph.D. degree (with honors) in computer science from the University of Paderborn in Germany in 1999 and 2003 (In the chair of Prof. Franz J. Rammig) respectively. In June 2003 he joined the department of computer science at the University of Erlangen-Nuremberg in Germany as Post doc, under the direction of Prof Jürgen Teich. Dr. Bobda received the best dissertation award 2003 from the University of Paderborn for his work on synthesis of reconfigurable systems using temporal partitioning and temporal placement. In 2005 Dr. Bobda was appointed assistant professor at the University of Kaiserslautern. There he set the chair for Self-Organizing Embedded Systems that he led until October 2007. From 2007 to 2010 Dr. Bobda was Professor at the University of Potsdam and leader of the working Group Computer Engineering. Upon moving to the US, Dr. Bobda was appointed Professor of computer engineering at the University of Arkansas where he founded the smart embedded systems lab (2010 – 2018). Since 2019, Dr. Bobda has been with the University of Florida as Professor of Computer Engineering, leader of the lab smart systems and outreach director of the Nelms Institute of Connected World.

Open-Source Frameworks for Building Heterogeneous SoCs and Reliable Reconfigurable Systems

Speaker: Dirk Koch - University of Manchester, UK

Abstract: This Talk will address the two core topics of the WRC 2021 workshop. 1) We will introduce our FABulous ecosystem for generating and programming of customizable embedded (FPGA) fabrics that can be easily integrated into own chips. We will present a case study that is integrating an eFPGA for custom instruction set extensions into a heterogeneous RISC-V SoC. 2) The second part of the talk will present how the GoAhead tool for implementing partially reconfigurable systems was used to build an adaptive and reliable system that can detect and mask defects on an FPGA. The system can change the layout of partial modules and can use different physical implementation variants for providing redundancy in the FPGA infrastructure (shell).

Short bio

Dirk Koch is a Reader in the Advanced Processor Technologies Group at the University of Manchester. His main research interests are on run-time reconfigurable systems based on FPGAs, embedded systems, computer architecture, VLSI and hardware security. Dirk developed techniques and tools for self-adaptive distributed embedded systems based on FPGAs. Current research projects include database acceleration using FPGAs-based stream processing, HPC and exascale computing, as well as reconfigurable instruction set extensions for CPUs and using FPGAs in datacenters. Dirk Koch is author of the book "Partial Reconfiguration on FPGAs" and a co-editor of the book "FPGAs for Software Programmers".

MC-DeF: Creating Customized CGRAs for Dataflow Applications

Speaker: Dionisis Pnevmatikatos - NTUA, Greece

Abstract: Executing complex scientific applications on Coarse Grain Reconfigurable Arrays (CGRAs) promises improvements in execution time and/or energy consumption compared to optimised software implementations or even fully customized hardware solutions. Typical CGRA architectures contain of multiple instances of the same compute module that consist of simple and general hardware units such as ALUs, simple processors. However, generality in the cell contents, while convenient for serving wide variety of applications penalises performance and energy efficiency. To that end, a few proposed CGRAs use custom logic tailored to a particular application’s specific characteristics in the compute module. This approach while much more efficient, restricts the versatility of the array. To date, versatility at hardware speeds is only supported with FPGAs, that are reconfigurable at a very fine grain. I will describe MC-DeF, a novel Mixed-CGRA Definition Framework targeting a Mixed-CGRA architecture that leverages the advantages of CGRAs by utilizing a customized cell-array, and those of FPGAs by incorporating a separate LUT array used for adaptability. The framework presented aims to develop a complete CGRA architecture. First a cell structure and functionality definition phase creates highly customized application/domain specific CGRA cells. Then mapping and routing phases define the CGRA connectivity and cell-LUT array transactions. Finally, an energy and area estimation phase presents the user with area occupancy and energy consumption estimations of the final design. MC-DeF uses novel algorithms and cost functions driven by user defined metrics, threshold values and area/energy restrictions. The benefits of our framework, besides creating fast and efficient CGRA designs, include design space exploration capabilities offered to the user. The validity of the presented framework is demonstrated by evaluating and creating CGRA designs of nine applications. Additionally we provide comparisons of MC-DeF with state of the art related works, and show that MC-DeF offers competitive performance (in terms of internal bandwidth and processing throughput) even compared against much larger designs, and requires fewer physical resources to achieve this level of performance. Finally, MC-DeF is able to utilize better the underlying FPGA fabric and achieves the best efficiency (measured in LUT/GOPs).

Short bio

Dr. Dionisios Pnevmatikatos *(male) received his B.Sc. in Computer Science from University of Crete in 1989 ad a M.Sc. and PhD degrees in Computer Science from the University of Wisconsin–Madison in 1991 and 1995 respectively. He is a Professor at the School of Electrical and Computer Engineering of the National Technical University of Athens. From 2000-2019 he was Professor at the School of Electrical and Computer Engineering, Technical University of Crete (TUC), where he served as Director of the Microprocessor and Hardware Laboratory (MHL) and as Chairman (one 2-year term). He is also a research associate with FORTH-ICS since 1997. He was the coordinator in FASTER FP7 EU project, and Principal Investigator in the DeSyRe FP7 and the AXIOM, dRedBox, EXTRA, and EDRAH2020 projects, as well as in several national projects. His research interests include Computer Architecture, with a focus on using reconfigurable computing to create highly efficient, accelerated, heterogeneous parallel/rack-scale systems. He has also worked on Reliable System Design, Networking Hardware and Network Processors, Application Acceleration, Custom and Application-Specific Architectures, and Hardware Acceleration of Bioinformatics Algorithms. He has been in the Program Committee of conferences such as ISCA, FPL and DATE in Computer Architecture and Reconfigurable System topics, and has been a Program (co)chair for SAMOS 2018 and FPL 2011.