IWDA'93:

Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analysed, and a corresponding set of testability building blocks are proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs, using a simple and powerful HDL.