Parallel Architectures and Compilation Techniques (PACT18), Limassol, Cyprus November 01-04, 2018

Tutorial: The ANTAREX Approach to Adaptively Optimize and Enforce Extra-Functional Properties on HPC Applications

Date: Nov. 3, 2018


Developing and optimizing applications for energy-efficient HPC systems up to the Exascale era is an extremely challenging problem. They are complex tasks that require mastering several programming languages and tools for performance tuning, which is incompatible with the trend to open HPC infrastructures to a wider range of users. The support of standard languages and APIs is crucial to provide migration paths towards novel heterogeneous HPC platforms as well as to guarantee the ability of developers to work effectively on these platforms. In this tutorial we show how the ANTAREX DSL-based approach allows developers to program and apply strategies (recipes) to applications in the context of extra-functional requirements, such as performance and energy-efficiency. We show our holistic and versatile approach spanning various decision layers composing the supercomputer software stack and exploiting effectively the system capabilities, including heterogeneity and energy management. Specifically, we present the ANTAREX toolflow to enable the definition of energy-efficiency, performance, and adaptivity strategies as well as their enforcement at runtime through application autotuning and resource and power management. Through representative case studies and a hands-on-approach, we show how the ANTAREX toolflow can effectively assist various development/optimization stages, including application analysis and profiling, code transformations and parallelization, and integration of monitoring and runtime autotuning.

Preliminary Program

14:30-14:40 Opening session, Cristina Silvano and João MP Cardoso
14:40-15:00 Overview of the ANTAREX Approach, Cristina Silvano, POLIMI, Italy
15:00-15:45 Monitoring and Control: the ExaMon and Countdown approach, Daniele Cesarini, Univ. of Bologna, Italy
15:45-16:30 Runtime Autotuning: the mArgot approach, Gianluca Palermo and Davide Gadioli, POLIMI, Italy
16:30-17:00 Coffee Break and Poster Sessions
17:00-18:00 DSL and Source to Source Compilation: hands-on-approach, Pedro Pinto and João MP Cardoso, UPORTO, Portugal
18:00-18:30 Summary of Lessons Learned and Main ANTAREX Achievements, Cristina Silvano, POLIMI, Italy
18:30-18:35 Closing session, Cristina Silvano and João MP Cardoso

Names and affiliations of main organizers

Main Topics

The exercises will be based on an example application that is relatively simple and known to the audience (e.g., matrix multiplication). We will use the LARA DSL and the Clava source to source compiler to apply increasingly more complex strategies over this initial example, starting with simple instrumentation strategies for measuring performance and energy, to performing design-space exploration and finally control the application with an autotuner.

We will show through a hands-on-approach how the tools and APIs provided by ANTAREX are able to efficiently and effectively help users/developers and how they can complement traditional tool flows.

The tools to be used during the tutorial are available at the following sites:

Short bios of the speakers

Cristina Silvano

Associate Professor (with tenure) of Computer Engineering at Politecnico di Milano. She received the M. Sc. Degree in Electrical Engineering from Politecnico di Milano in 1987 and the Ph. D. Degree in Computer Engineering from University of Brescia in 1999. From 1987 to 1996, she was Senior Designer at Group Bull joining the Bull-IBM Research team for the design of a family of scalable multiprocessor systems based on the PowerPC architecture, introduced in 1992 by Apple-IBM-Motorola. Since 1996, she started a continuous research collaboration with STMicroelectronics and she was Principal Investigator of two industrial research projects funded by STMicroelectronics (2003-2008). Her current research interests are in the design of energy-efficient computer architectures with special emphasis on design space exploration and application autotuning for embedded manycore architectures. In these areas, she has coordinated two EU-funded projects (MULTICUBE and 2PARMA). She is also active in the area of autotuning and adaptivity for energy-efficient High Performance Computing systems. On this topic, she is currently the Scientific Coordinator of the H2020 FET-HPC ANTAREX research project. She is an active contributor to the scientific community and she regularly serves as Member (or Track Chair) of the Program Committee of severa conferences such as ICCAD, DAC, DATE, NOCS, HPCA, MICRO, ASAP, FPL. Recently she was Program Chair of FPL 2015, the 25th International Conference on Field Programmable Logic and Applications. She was Program Co-Chair of ASAP2012, ARC2011, and SASP2010. She was General Co-Chair of SASP2009 and MICRO2008 (receiving the ACM Recognition of Service Award). She is Associate Editor of the ACM Transactions on Architecture and Code Optimization. She served as independent expert reviewer for the European Commission and for several science foundations. She has published more than 160 publications in peer-reviewed international journals and conferences, four books and has made several industrial patent applications. She has been named an IEEE Fellow (since 2017) from the IEEE Board of Director “for contributions to energy-efficient computer architectures”. She is member of ACM and member of HiPEAC Network of Excellence.

João MP Cardoso

Full Professor at the Department of Informatics Eng., Faculty of Eng. of the Univ. of Porto, Porto, Portugal and a research member of INESC TEC. Before, he was with the IST/UTL (2006-2008), a senior researcher at INESC-ID (2001-2009), and with the Univ. of Algarve (1993-2006). He has been involved in the organization and served as a PC member for many Intl. Conferences. He is General Co-Chair of DASIP’2018, he was general Co-Chair of IEEE/IFIP EUC’2015 and IEEE CSE’2015, General Chair of FPL’2013, General Co-Chair of ARC’2014 and ARC’2006, Program Co-Chair of ARCS’2016, DASIP’2014, and RAW’2010. He has (co-)authored over 200 scientific publications on subjects related to compilers, DSLs, embedded computing, and reconfigurable computing. He has participated in a number of research projects: as co-scientific coordinator of the FP7 EU-funded project REFLECT (2010-2012), and as coordinator of a number of national funded projects. He is a senior member of IEEE, a member of IEEE Computer Society, and a senior member of ACM. His research interests include compilation techniques, domain-specific languages, and HPC with a particular emphasis in embedded computing.

Daniele Cesarini

Last year Ph.D. student in the Department of Electrical, Electronic and Information Engineering, University of Bologna. His research interests include parallel programming models and energy-efficient runtimes for embedded and HPC systems. He is the main responsible for the development of the power management libraries in the ANTAREX project.

Pedro Pinto

PhD student in Informatics Engineering at the Faculty of Engineering of the University of Porto. At the end of 2012, Pedro Pinto obtained his MSc from the same institution. Since graduating, Pedro Pinto has been involved in several research projects in the area of compilers, including source-to-source compilation and the specification of strategies to identify program faults or to instrument code for profiling. His main research interests are directly related to his work and include source-to-source compilation, dynamic and static code analysis as well as optimizations and code transformations. Finally, his interests also include broader topics such as programming languages, high-performance computing and machine learning.