Energy proportional binarized neural networks with adaptive voltage and frequency scaling

Jose L. Nunez-Yanez

Speaker: Jose L. Nunez-Yanez, Bristol University.

Abstract: This research presents the application of an extended voltage and frequency scaling framework called Elongate to a high-performance and reconfigurable binarized neural network. The neural network is coupled to a multiprocessor system-on-chip that acts as a host controlling the operational point to obtain energy proportionality. Elongate instruments a design netlist by inserting timing detectors to enable the extension of the operating margins of a design reliably. The elongated neural network is scaled up and re-targeted to devices with different nominal operating voltages and 28nm/16nm processes showing the portability of the Elongate framework to advanced process nodes. New hardware and software components are created to support the new reconfigurable fabrics. The results show that Elongate can obtain new performance and energy points that are up to 80% better than nominal at the same level of classification accuracy. The results also indicate that the built-in neural network robustness allows operation beyond the first point of error while maintaining the classification accuracy largely unaffected.

Short bio

Jose L. Nunez-Yanez is a Reader in Adaptive and Energy Efficient computing in the department of Electronic Engineering at Bristol University, UK. Prior to that he was a research fellow in the department of Electronic Engineering at Loughborough University, UK where he worked from 1997 until 2004 obtaining his PhD degree in 2001 working on the area of hardware architectures for high-speed lossless data compression. During 2005 and 2006 he worked in ST Microelectronics, Italy with a Marie Curie fellowship in the area of reconfigurable processors for video coding and in 2011 he was a Royal society fellow at ARM, Cambridge in system-level power modelling. His current research interests include the areas of lossless data compression, video/signal processing, reconfigurable and adaptive computing for low power and hardware acceleration architectures. He received his BEng and MEng degrees in Electronics Engineering from Universidad de La Coruna (La Coruna, Spain) and Universidad Politécnica de Cataluña (Barcelona, Spain) respectively in 1993 and 1997.

Tool-flows for mapping CNNs into FPGAs: Trends and Challenges

 Christos Bouganis

Speaker: Christos Bouganis, Imperial College London.

Abstract: Machine Learning algorithms, and in particular Convolutional Neural Networks or CNNs, have attracted the attention of many research communities due to their excellent performance in a number of computer-vision related tasks. Reconfigurable Computing in the form of FPGAs, promises high performance implementations of the above systems with a low power consumption. Nevertheless, the long production cycle of hardware design, combined with the large design space of modern FPGAs deter practitioners from targeting those devices. The presentation will focus on modern design tool-flows that aim to automate the mapping of a CNN into a target FPGA device, paving as such the way for the easily adoption and fast deployed of FPGA-based CNN systems. The presentation will highlight the current trends in this area, it will discuss the challenges in producing such tool-flows, and it will provide an insight of the future in this area.

Short bio

Dr. Bouganis is a Senior Lecturer in the Department of Electrical and Electronic Engineering at Imperial College London, leader of the Intelligent Digital Systems Lab (iDSL), and the MSc Director of Analogue and Digital Integrated Circuit Design (MSc ADIC). His main research interests include the theory and practice of reconfigurable computing and design automation, mainly targeting digital signal processing algorithms in the areas of Computer Vision, Machine Learning, and Bayesian Inference.

Ultra-low power features of Nema GPUs

Speaker:Georgios Keramidas, Think Silicon S.A., Greece.

Abstract: Dealing with the levels of power consumption required by wearables and Internet of Things (IoT) devices represents a major technological challenge that demands multi-disciplinary approaches spanning circuit, architecture, compiler, and API level optimization techniques. The main challenge in these new devices is the battery life and how to extend it to more than one day without having to search for wall plugs and charging stations. Thus, ultra-low power devices performing energy-conscious graphics calculations are desperately needed in the market. This presentation will focus on the co-design SW-HW technology developed by Think Silicon, realized in the current products of the company (Nema|S, Nema|t and Nema|p; the world smallest 2D/3D GPUs in the market), targeting to set forward a set of low power techniques working in a synergistic fashion. As part of this presentation, we will also discuss Think Silicon’s effort in mapping image, vision, and NN applications in a heterogeneous, multicore architecture consisting of 3 types of Nema GPUs targeting mainly the low-end and edge computing market.

Short bio

Dr. Georgios Keramidas currently serves as chief architect of the multi-core and highly multi-threaded Nema GPU. He has a successful track record in delivering commercial projects as well as national and collaborative programmes. During the last years, Dr. Keramidas has participated in seven research projects funded by European Commission and in three national projects either as scientific advisor, main researcher, or project coordinator. Dr. Keramidas is also a visitor assistant professor at the Technological Educational Institute of Western Greece and at University of Patras teaching courses in computer architecture, embedded systems, and real-time OS. Dr. Keramidas’ main research interests are in the areas of low-power processor/memory design, multicore systems, network and graphic processors, reconfigurable systems, and fault-tolerance systems. He has published more than 60 scientific papers, one book, and he also holds six granted US patents (three more patents are under evaluation). His work received more than 600 citations. He is a member of ACM and HiPEAC and a regular reviewer and PC member in high-quality conferences, workshops, and transactions.

Multi-level control of reconfigurable architectures for autonomous vehicles

Jean-Philippe Diguet

Speaker: Jean-Philippe Diguet, CNRS, Lab-STICC

Abstract: Reconfigurable computing is solution to optimize the energy efficiency of embedded systems since it allows to dynamically select dedicated hardware accelerators according to the demand of applications. Autonomous vehicles and ADAS systems require high performances under strong SWaP constraints, however they also must be fully reliable so dynamic hardware reconfiguration must be validated. In the HPeC project we consider a multi-level approach that relies on a formal approach to meet this constraint. We propose an autonomic control architecture for self-adaptive and self-reconfigurable FPGA-based embedded systems. The control architecture is structured in three layers: a mission manager, a reconfiguration manager and a scheduling manager. In the talk we will focus on the design of the reconfiguration manager, which is based a design approach using automata-based discrete control.

Short bio

Jean-Philippe Diguet is a CNRS director of research at Lab-STICC, Lorient/Brest, France. He received the Ph.D degree from Rennes University (France, 96), was a postdoc at IMEC (Belgium, 1997) and an associate professor at UBS (France, 97/03). After a technology transfer, he joined the CNRS as a researcher in 2004. He has been a visitor researcher at UQ (Australia, 2010) and invited Prof. at Tohoku University, (Japan, 2014) and at USP (Brazil, 2016). His work targets various aspects of embedded system design: Self-adaptive SoC, CAD tools for heterogeneous MPSoC, IP design in various domains and smart NoC. Since 2015 Nov. he is leading the HPeC Project dedicated to Adaptive SoC for Autonomous vehicles.

Reconfigurable Embedded Systems for Autonomous Driving

Smail Niar

Speaker: Smail Niar, University of Valenciennes & CNRS

Abstract: The automotive industry continues to look at ways to reduce the fatalities and the severity of road accidents. To achieve this, Advanced Driver Assistant Systems or the future Autonomous Driving Systems, that are expected to be largely present in our roads by 2050 have attracted great interest both in academia and industry. Lane-departure warning, road extraction, obstacle detection and tracking are among the functionalities that will be largely used in future cars. In this presentation, I will talk about existing approaches for some of these functionalities in Advanced Driver Assistant Systems (ADAS) and Autonomous Driving (AD). The use of dynamic and partial reconfiguration to modify the HW will be explored. The purpose is to dynamically and automatically tune the system architecture to match the characteristics of the operational environment. Compared to alternative solutions, field-programmable gate array (FPGA) based reconfigurable architectures lead to reduce total cost and power consumption. Decreasing energy consumption, first minimizes hardware complexity and enables to fit the system in a smaller FPGA. Second, higher power consumption leads to higher temperature, which, in turn, reduced system robustness and reliability.

Short bio

Pr. Smail Niar (University of Valenciennes & CNRS, France) received his PhD in computer Engineering from the University of Lille (France) in 1990. Since then, he has been professor at the University of Valenciennes where he is member of the “Mobile & Embedded Systems" research group at the “Laboratory of Automation, Mechanical and Computer Engineering”, a joint research unit between CNRS and the university of Valenciennes. S.Niar co-supervises the «Intelligent infrastructures & vehicles » task within the International Campus on Safety and Inter-modality in Transportation (“Campus International sur la Sécurité l’Intermodalité dans les Transports” CISIT). Prof. S.Niar is member of the editorial board at the “Embedded Hardware Design: Microprocessors and Microsystems” (Elsevier) journal. He is member of the European Network of Excellence on “HIgh Performance and Embedded Architectures and Compilation” (HIPEAC), EuroMicro society and IEEE senior member. His research interests are in heterogeneous multi-processor system-on-chip (MPSoC) architectures in intelligent transportation systems, power/energy consumption optimization, dynamically reconfigurable embedded systems (FPGA) and reliability issues for embedded systems.

Convolutional Neural Networks on embedded systems: an exploratory study

Paolo Burgio

Speaker: Paolo Burgio, Università degli Studi di Modena e Reggio Emilia - UNIMORE

Abstract: Convolutional Neural Networks (CNN) are widely adopted today in different application domains, from image categorization for medical applications, to industrial computer vision systems, to autonomous driving systems, and semantic analysis. At the same time, heterogeneous embedded platforms represent the ideal choice to power up these systems, meeting both their tight SWaP (Size, Weight and Power) and Performance/Watt requirements. There are currently several "flavours" of such platforms, ranging from reconfigurable, FPGA-based platforms, to high-performance GPU-based systems, to more flexible many-core based systems. We will compare several CNNs running on different platforms, characterizing them in terms of performance/Watt and accuracy/Watt, ultimately assessing their effectiveness when adopted in the next-generaion of embedded systems.

Short bio

Paolo Burgio got a Ph.D in Electronics Engineering jointly between the University of Bologna and the University of Southern-Brittany, in 2013. His research topics are next-generation predictable systems based on heterogeneous many-cores and GP-GPUs, with an eye on compilers, and parallel programming models. Since 2014 he joined HiPeRT at Univ. of Modena where he currently works on autonomous driving systems. Paolo is currently involved in Hercules and Enable-S3 H2020 projects.

Are FPGAs ready for accelerating datacenters

Dirk Koch

Speaker: Dirk Koch, Friedrich-Alexander-University of Erlangen-Nürnberg, FAU

Abstract: Technology is commonly driven by markets and the corresponding target application domains. In the case of FPGAs, networking, industrial and embedded systems were traditionally driving technology and consecutively the development of new devices and tools. However, the arise of cheap large capacity data storage and fast Internet has lead into the big data era where data processing is now that demanding that acceleration is basically inevitable. Mostly driven by machine learning and data analytics where the amount of compute per unit of data is colossal, many datacenters are now under a transition to become accelerator centric. While prominent examples from Microsoft, Amazon and Alibaba demonstrate that this is well including FPGAs, this movement is happening much faster than the development of FPGA technology, design methods and tools are currently catching up and the whole FPGA ecosystem, including industry and research is under tremendous pressure to deliver or to become a one-hit wonder. This talk will look into the requirements on FPGA hardware platforms, design methodologies and tools as needed for FPGA general purpose acceleration in datacenters. It will show where we are and what is still needed but also some solutions and recent research to get there. This will include aspects such as automated physical high-level module implementation and FPGA virtualization for cloud environments.

Short bio

Dirk Koch is a lecturer in the Advanced Processor Technologies Group at the University of Manchester. His main research interest is on run-time reconfigurable systems based on FPGAs, embedded systems, computer architecture and VLSI. Dirk developed techniques and tools for self-adaptive distributed embedded control systems based on FPGAs. Current research projects include database acceleration using FPGAs-based stream processing, HPC and exascale computing, as well as reconfigurable instruction set extensions for CPUs. Dirk Koch is author of the book "Partial Reconfiguration on FPGAs" and a co-editor of the book "FPGAs for Software Programmers" and his group is developing and maintaining the GoAhead framework that provides unique capabilities for building run-time reconfigurable systems.

Next Generation Automotive Networks for ADAS and Autonomy

Suhaib Fahmy

Speaker: Suhaib Fahmy, School of Engineering, University of Warwick

Abstract: The demands of advanced driver assistance systems and autonomous driving significantly exceed the capabilities of traditional in-car networks, which has led to efforts to rethink how such networks are designed. Such systems rely on large volumes of sensor data being channeled for low-latency decision making which is at odds with the traditional designs geared around high throughput for non-critical AV applications and high-reliability but low-throughput for critical applications. This talk will explore two approaches to address these challenges. First, we discuss the concept of smart network controllers that are able to process data without processor intervention to enhance network capabilities. Next we explore the design of automotive switches for bridging together modern networks with legacy systems while maintaining reliability. The two approaches are validated in real FPGA prototypes that will be discussed.

Short bio

Suhaib Fahmy leads the Connected Systems Research Group in the School of Engineering at Warwick and is a Turing Fellow with The Alan Turing Institute. He graduated with an MEng and PhD from Imperial College London in 2003 and 2008, respectively, followed by time with Trinity College Dublin and Xilinx Research Labs, and 6 years with Nanyang Technological University in Singapore. His research explores the use of reconfigurable systems in domains including communications, cyber-physical systems, and automotive networks. Dr Fahmy received the Best Paper Award at FPT 2012, the IBM Faculty Award in 2013 and 2017, and the Community Award at FPL 2016. He serves on the technical program committees for a number of prestigious conferences in the area of reconfigurable computing, actively reviews for many journals in related areas, and sits on the ACM Technical Committee on FPGAs.