Relatório ESPRIT R4.4:

Sumário:

Report R4.4 presents the verification of TPG procedures for BST boards where additional (simple-to-test) clusters of non-BST components may be present. These clusters are restricted to low-complexity combinational blocks of logic (and eventually low-depth sequential circuits) and to regular structure blocks, like RAM or ROM memories. This document results from the work done in task 4.2.3 and is related to the work described in report R4.2 and in deliverables D4.4, D4.7 and D4.11.

Índice:

1 – INTRODUCTION

2 – TESTING BOARDS WITH ADDITIONAL ST-CLUSTERS

Test access
    Virtual interconnect testing
    Standard cluster testing
    Virtual cluster testing
Test pattern generation
    Ad hoc methods
    TPG for the general case
Fault coverage assessment

3 – TEST PROTOCOL FOR THE GENERAL CASE

BIT infrastructure test
    OBTPs support BIST
    OBTPs without BIST
Interconnect test
Components test

4 – A CASE STUDY

Circuit description
Cluster access description files
Test pattern description files
Test program specification in BITL
    BIT infrastructure test
    Interconnect test
        Full BST interconnects
        Cluster interconnects
    Component test

5 – CONCLUSION

REFERENCES

APPENDIX A: Schematic of the demonstration board

APPENDIX B: EDIF description of the demonstration board