Relatório ESPRIT D4.2:

Sumário:

This document presents a high level pseudocode specification of a set of test pattern generation (TPG) procedures for testing interconnects in boards loaded exclusively with BST components, where more than one BST chain may exist.
The characteristics of the adopted board-level fault model are briefly described. Open, stuck-at and short faults are considered, and the underlying technology related assumptions are presented.
For interconnect short testing, a two-step algorithm is presented. In the first step, a minimum size set of test patterns (TPs) with full fault detection capability is used. The concept of Eventually Puzzling Syndromes is introduced and is used to specify a reduced complexity second step, allowing complete fault location.
The TPG procedures for detection and diagnosis of the various fault types are presented in a high level C language type pseudocode.

Índice:

1 – INTRODUCTION

Interconnects and test points in F-BST boards
The fault model and its influence on TPG

2 – TEST PATTERN GENERATION

The generation of test patterns for open and stuck-at faults
The generation of test patterns for short faults
    The case for adaptive algorithms
    Comparison of TPG algorithms for the first step
    Eventually Puzzling Syndromes
An adaptive algorithm for interconnect short fault testing
    Tester requirements
    Application example
TPG when more than one BST chain exists
The complete TPG algorithm
    An example

3 – HIGH LEVEL SPECIFICATION OF THE TPG PROCEDURES

The information required by TPG procedures
Specification of all TPG procedures
    TPG for complete fault detection, partial fault diagnosis
    TPG for complete fault diagnosis

4 – CONCLUSIONS

5 - REFERENCES