Publicações
internacionais
Sumários
e Índices
Publ. pedagógica LEONARDO DfTSPS:
Sumário:
This Design for Test Standards and Proposed Standards text belongs to
the set of deliverables under the responsibility of FEUP and is intended
to guide an applications-oriented approach to the area of testable circuits
design. It is important to emphasise the applications-oriented approach
underlying the development of this course material, essentially intended
to be used in a laboratory environment, more than in a classroom environment.
Hands-on exercises are therefore proposed at the end of some of its chapters,
with more to be added in the near future.
Two types of additional resources are required to support the hands-on
sessions:
-
A hardware complement to this text, in the form of a demonstration board
that illustrates in practice the problems and possible solutions related
to testing circuits with boundary scan.
-
A Windows application that enables the students to write and execute their
own test programs.
The necessary information for manufacturing demonstration boards is attached
as an annex at the end of chapter 5 (A case study of test program execution)
and a set up diskette for the Windows boundary scan test controller application
is included at the end of this document.
While the general principles of scan-based design for testability are
de facto standards coming from the late 70s, the approval in 1990 of the
IEEE 1149.1 boundary scan architecture and test access port greatly improved
industry acceptance and made scan design techniques accessible to any designer.
Greater relevance is therefore given to the IEEE 1149.X suite of design
for test standards and proposed standards, with updates to be added as
later releases of this text become available.
Índice:
1 - BASIC TEST CONCEPTS
Fault modeling and ss@ faults
Controllability, observability and testability
Test vector generation for combinational circuits
Testability and test generation in sequential circuits
Testability improvement via ad hoc solutions
Structured approaches to design for testability
2 - THE BOUNDARY SCAN TEST (BST) TECHNOLOGY
The development of BST and its application domain
The BS architecture and test access port (TAP)
The basic boundary scan cell
The test data registers
The instruction register
The TAP controller
3 - TEST PROTOCOL FOR BST BOARDS
Fault detection in the BS infrastructure
Open fault detection in full-BST interconnections
Short-circuit fault detection among full-BST interconnections
Full-BST interconnect testing in boards with multiple BS chains
Fault detection in non-BS clusters
Testing non-BS clusters in boards with multiple BS chains
Faulty components detection
4 - A BS TEST CONTROLLER MODEL
Basic test operations
Basic test operations to control the BS infrastructure
Basic test operations to synchronise the BS infrastructure
with external test resources
Basic test operations to control internal resources
and test program flow
The test instruction set
Control of the BS infrastructure
Synchronisation with external test resources
Control of internal resources and test program flow
Test program generation
5 - A CASE STUDY OF TEST PROGRAM GENERATION
The demonstration board
The information required for test program generation
Integrity check of the BS infrastructure
Full-BS interconnects test
Non-BS clusters test
Components test
The test vectors
Test vectors for short-circuit detection in full-BS
interconnects
The complete set of serialised test vectors, expected
responses and mask data
The test program
6 - A WINDOWS BS TEST CONTROLLER APPLICATION
Test set up
The test controller application
Test program control bar
Status information
Pop-down menus
Editing area
Application set up
7 - INTRODUCTION TO MIXED-SIGNAL TESTING USING THE P1149.4 STANDARD
Scope of the IEEE P1149.4 standard
P1149.4 Overview
The basic 1149.4 architecture
P1149.4 test register structure
P1149.4 instructions
P1149.4: The main blocks
The Test Bus Interface Circuit (TBIC)
The Analog Boundary Modules (ABM)
Interconnect testing with P1149.4
Impedance measurements with P1149.4
Impedance between pin and ground
Impedance between two pins
P1149.4: Further information
|