DAK-forum 2004:

Fault-tolerant (FT) architectures based on classic spatial and temporal redundancy are used in an increasing number of applications. However, the hardware platforms underlying modern high-reliability systems have little resemblance to those that were common when such architectures were devised. The earlier fault models are not necessarily out-of-date (e.g. stuck-at faults still play an important role for validating FT applications), but the new failure modes of nanometer technologies were largely irrelevant when J. von Neumann’s paper on the synthesis of reliable organisms from unreliable components was published in the 1950s. Such concerns are particularly relevant when designing high-reliability adaptive systems, where reconfigurable field-programmable gate arrays (FPGAs) are increasingly used. On the other hand, the economics of FT architectures based on spatial redundancy (e.g. triple modular redundancy, TMR), are entirely different when evaluated under the assumption of such features as dynamic reconfiguration, which enables just-in-time implementation of only those resources that need to be available at any given time, or self-reconfiguration, which enables self-contained corrective actions that are able to isolate / replace defective resources. New design approaches are therefore required to cope with the challenges introduced by each new generation of programmable hardware devices. This paper presents an approach to design high-reliability architectures at lower cost, by taking advantage of dynamic / self reconfiguration and built-in test infrastructures, which are present in modern generations of FPGAs.