FPGAs (Field Programmable Gate Array) are programmable logic devices that were introduced with the main objective of shortening the larger time-to-market cycles that were common with application-specific solutions (ASICs, Application-Specific Integrated Circuits). Ever since their market introduction in the early 1980s, the integration scale and complexity of FPGAs has grown sharply. An important milestone in the technology roadmap of such components was the introduction of devices featuring partial and dynamic reconfiguration, which enabled new applications in several domains, and not the least the development of innovative testing approaches for products based on this recent technology.

This document describes a set of tools that support the application of a non-intrusive online concurrent test strategy presented by Manuel Gericota in [Gericota 2003]. The tools that were developed carry out the partial and dynamic reconfiguration of Virtex FPGAs, and other tasks required by the test strategy referred above, namely the replication of active logic blocks (i.e. logic blocks that are actually being used by applications that are currently running) and the re-routing operations required for this purpose. These tools also enable the development of further applications that exploit the partial and dynamic reconfiguration features of these devices.